component: keygen.vhd

Component serves as an intelligent key generator. As discussed in earlier discussion, exhaustively testing a 56 bit keyspace at 50MHz would take 16.6 thousand days. We have therefore decided to reduce our pool to keys consisting of alpha numeric characters encoded un UTF-8. This was made in an attempt to exploit the greatest wekness of any encryption algorithm: human behavior predictability. The key generator also starts by scanning capital letters as a first digit (in yet another attempt to benefit from people using a name as an encryption key). The first key is "Aaaaaaa", followed by "Aaaaaab" ans generates one key every clock pulse until it reaches "zZZZZZZ".

By doing this reduction, our testing space has been reduced from 2^56 = 7.2E16 to 62^7 = 3.5E12 (i.e. by a factor of 2,000). Using a 50MHz clock this list can be exhausted in 9.8 hours on average or 19.5 hours worst case. (3.5E12 keys / 50MHz / 3600 seconds/Hours). If we acchieve a clock speed of 100MHz and are able to fit 2 decrypting devices within a single FPGA, the processing time can be reduced to 2.4 hours.


component: lookup.vhd

The basic principle of a brute force attack is to try and decrypt a message with every possible key compinations to assure a positive result. Once the encrypted data has been decrypted with a given key, a secondary component validates this data to look for coherence. One could use character statistical analysis matched with the sender's language letter frequency analysis, a dictionary lookup component, or any previous knowledge of the encrypted message. (For example, during WWII, the allies would match the final characters of encoded messages with "Hail Furer"). 

In our case, we will assume that the encrypted data is a letter addresses to Professor Gross, and therefore starts with "Dear Gross". Since the data in encrypted in blocks of 64 bits, we will match the decrypted data with "Dear Gro". The lookup unit inputs the decrypted data and asserts the match line if a potential match is found.



component decrypter.vhd

This is the whole decrypter put together. Besides a clock and reset, it inputs a 64 bit data vector to be decrypted. When receiving an encrypted message, we will use the fisrt 64 bits of the cyphertext and assume they are "Dear Gro" (as explained above". The decrypter follows the DES encryption standarard to decryps the data and outputs the key used once a match is found.

The decrypter has been pipelined into 18 stages. The first and last stages are the initial and final permutation, and the 16 remaining stages are the encryption stages (XOR of L, R and the 'F' functions) which use a sub key generated by the key scheduler. All the logic in the stages is purely asynchreneous, and the timing is acheived by the clocked registers placed between each stage.














Simon Foucher's contribution:
Generated and debugged the VHDL code for keygen.vhd, lookup.vhd and decrypter.vhd. Also wrote the related documentation in the report.