TEAM: Shajib Sadhukha, Yvan Tonthat, Simon Foucher

Title: Pipelined design to conduct brute force attacks on DES block cipers

Abstract: Brute force cryptic attacks guarantee results but often require overwhelming amounts of time. Since DES uses block cypher encryption instead of arithmetic algorithm, it has been proven to be vulnerable to attacks conducted by decryption specific hardware which can easily be implemented on FPGAs. By pipelining the 19 DES encryption stages, an FPGA can exhaust all possible 56 bit keys in 16.7 days worst case running on a 50MHz clock. In this paper, we describe how we designed a DES decrypting pipeline processing keys intelligently generated to take advantage of common human weaknesses. The cypher data used to test the device was assumed to be mostly plain ASCII text. The decyphered data was then fed into an ASCII LUT to be validated. If a match was found, the key was recorded as potentially good and data to be validated by a human. We evaluated the hardware speed up provided by the design compared to a software equivalent, as well as the cost, performance and feasibility of using many board in parallel to achieve a faster result.


References:

Clayton, Richard and Mike Bond, "Experience Using a Low-Cost FPGA Design to Crack DES Keys", University of Cambridge, Computer Laboratory, Gates Building, JJ Thompson Avenue, Cambridge, United Kingdom

Hamer, Ivan and Chow, Paul "DES Cracking on the Transmogrifier 2a", Department of Electrical and Computer Engineering, University of Toronto

Nazar A. Saqib, Francisco Rodrıguez-Henriquez, and Arturo Dıaz-Perez, "A Compact and Efficient FPGA Implementation of the DES Algorithm", Computer Science Section, Electrical Engineering Department, Centro de Investigacion y de Estudios Avanzados del IPN



Web:
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