g07_Flasher_Testbed PORTS:



Reset,CLK, EN : in std_logic;
Freq_Sel: in std_logic_vector(1 downto 0);
segment3,segment2,segment1,segment0 : out std_logic_vector(6 downto 0);
RippleBlank_Out: out std_logic );






circuit	:Board		:	Displays
segment3:HEX3LEFTMOST	:	E
segment2:HEX2		:	r
segment1:HEX1		:	r
segment0:HEX0RIGHTMOST	:	BLANK


Switches assignment
CLK	:PIN_D12INTERNAL	: INTERNAL CLOCK
EN	:SW[9]LEFTMOST		: Enables the circuit
RipBlkIN:SW[8]SecondLETMOST	: Enables RIpple Banks in
Freq_Sel:SW[0]SW[1]RIGHTMOST	: Toggles flashing frequency
RipBlkOPUT:REDLED[0]RIGHTMOST	: